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OKI Semiconductor ML7074-001 GA
VoIP CODEC
FEDL7074-001DIGEST-01
Issue Date: Oct. 15, 2002
GENERAL DESCRIPTION
The ML7074-001GA is a speech CODEC for VoIP. This LSI allows selection of G.729.A, G.726, or G.711 standard as a speech CODEC. The LSI is optimum for adding VoIP functions to TAs, routers, etc., since it has the functions of an echo canceller for 32 msec delay, DTMF detection, tone detection, tone generation, etc.
FEATURES
* Single 3.3 V power supply operation (DVDD0, 1, 2, AVDD: 3.0 to 3.6 V) * Speech CODEC: Selectable among G.729.A (8 kbps), G726 (32 kbps), G.711 (64 kbps) -law, and A-law Mutual conversion function between G.729.A (8 kbps) and G.726 (32 kbps). * Echo canceller for 32 ms delay * DTMF detect function * Tone detect function: 2 systems (1650 Hz, 2100 Hz: Detect frequency can be changed.) * Tone generate function * FSK generate function * Dial pulse detect function * Dial pulse transmit function * Internal 1-channel 16-bit timer * Built-in FIFO buffers (640 bytes) for transferring transmit and receive data Frame/DMA (slave) interface selectable. * Master clock frequency: 4.096 MHz (crystal oscillation or external input) * Hardware or software power down operation possible. * Analog input/output type: Two built-in input amplifiers, 10 k driving Two built-in output amplifiers, 10 k driving * Package: 64-pin plastic QFP (QFP64-P-1414-0.80-BK)
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TONE_DET0
TONE0_DET TONE1_DET DTMF_DET DTMF_CODE[3:0]
TONE_DET1 DTMF_REC Speech Codec Echo Canceller Encoder G.729.A
TXGAIN Sin LPAD Sout
OKI Semiconductor
GSX0 Bus Control Unit
BLOCK DIAGRAM
10k
AIN0N
BPF
Linear PCM Codec G.726 G.711 G.729.A TX Buffer1 TX Buffer0
AIN0P + ATTs STGAIN Center Clip GPAD
AMP0
A/D
GSX1
10k
AIN1N AFF Decoder G.729.A
LPF
Rout ATTr RXGAIN Rin
AMP1
TONE_GEN (TONEA/B)
10k
VFRO0 G.711 FSK_GEN G.729.A
D/A
G.726
RX Buffer0 RX Buffer1 8b A0-A7 16b
Frame/DMA Controller
AMP2
10k
VFRO1
AMP3
Codec Decoder
G.711 G.726
AVREF
VREF
PCMI
S/P
TIMER DPGEN PLL CKGN
MCK SYNC(8kHz)
CR17-B0(GPO0) CR16-B0(GPI0)
Encode r
G.711
PCMO
G.726
P/S
DPDET
Control Register
D0-D15 CSB RDB WRB FR0B FR1B ACK0B ACK1B
SYNC OSC
BCLK
Power
DP_DET DTMF_DET DTMF_CODE[3:0] TONE0_DET TONE1_DET DP_DET
INT
INTB
CLKSEL XI XO
Serial I/F PDNB TST0 TST1 TST2 TST3 DVDD1 DVDD0 DGND0 DGND1 DVDD2 DGND2 AGND AVDD GPI0 GPI1 GPO0 GPO1
FEDL7074-001DIGEST-01
ML7074-001 GA
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PIN ASSIGNMENT (TOP VIEW)
43 CLKSEL
44 DGND1
AVDD 49 AIN0P 50 AIN0N 51 GSX0 52 GSX1 53 AIN1N 54 AVREF 55 VFRO0 56 VFRO1 57 AGND 58 DGND2 59 XI 60 XO 61 DVDD2 62 TST3 63 TST2 64 FR0B 10 FR1B 11 INTB 12 CSB 13 RDB 14 WRB 15 DGND0 16
1 2 3 4 5 6 7 8 9
33 DVDD1 32 D15 31 D14 30 D13 29 D12 28 D11 27 D10 26 D9 25 D8 24 D7 23 D6 22 D5 21 D4 20 D3 19 D2 18 D1 17 D0
48 GPO1
47 GPO0
42 PDNB
46 GPI1
45 GPI0
41 A7
40 A6
39 A5
38 A4
37 A3
36 A2
35 A1
ML7074-001
SYNC
BCLK
DVDD0
PCMO
PCMI
ACK0B
64-pin plastic QFP
ACK1B
TST1
TST0
34 A0
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PIN DESCRIPTIONS
Pin No. 1 2 3 4 5 Symbol TST1 TST0 PCMO PCMI BCLK I/O PDNB = "0" I I O I I/O "L" I 6 7 8 9 10 SYNC DVDD0 ACK0B ACK1B FR0B (DMARQ0B) I/O "L" I I O I I "H" "0" "0" "Hi-z" I I Description Test control input 1: Normally input "0". Test control input 0: Normally input "0". PCM data output PCM data input CLKSEL = "0" PCM shift clock input CLKSEL = "1" PCM shift clock output CLKSEL = "0" PCM sync signal 8 kHz input CLKSEL = "1" PCM sync signal 8 kHz output Digital power supply Transmit buffer DMA access acknowledge signal input Receive buffer DMA access acknowledge signal input FR0B: (CR11-B7 = "0") Transmit buffer frame signal output DMARQ0B: (CR11-B7 = "1") Transmit buffer DMA access request signal output FR1B: (CR11-B7 = "0") Receive buffer frame signal output DMARQ1B: (CR11-B7 = "1") Receive buffer DMA access request signal output Interrupt request output "L" level is output for about 1.0 sec when an interrupt is generated. Chip select control input Read control input Write control input Digital ground (0.0 V) Data input/output Data input/output Data input/output Data input/output Data input/output Data input/output Data input/output Data input/output Data input/output Fix to input state when using in 8-bit bus access (CR11-B5 = "1").
11
FR1B (DMARQ1B) INTB CSB RDB WRB DGND0 D0 D1 D2 D3 D4 D5 D6 D7 D8
O
"H"
12 13 14 15 16 17 18 19 20 21 22 23 24 25
O I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O
"H" I I I I I I I I I I I I I
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26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
D9 D10 D11 D12 D13 D14 D15 DVDD1 A0 A1 A2 A3 A4 A5 A6 A7 PDNB
I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I
I I I I I I I I I I I I I I I "0"
43 44 45 46 47 48 49 50 51 52 53 54 55
CLKSEL DGND1 GPI0 GPI1 GPO0 GPO1 AVDD AIN0P AIN0N GSX0 GSX1 AIN1N AVREF
I I I O O I I O O I O
I I I "L" "L" I I "Hi-z" "Hi-z" I "L"
Data input/output Fix to input state when using in 8-bit bus access (CR11-B5 = "1"). Data input/output Fix to input state when using in 8-bit bus access (CR11-B5 = "1"). Data input/output Fix to input state when using in 8-bit bus access (CR11-B5 = "1"). Data input/output Fix to input state when using in 8-bit bus access (CR11-B5 = "1"). Data input/output Fix to input state when using in 8-bit bus access (CR11-B5 = "1"). Data input/output Fix to input state when using in 8-bit bus access (CR11-B5 = "1"). Data input/output Fix to input state when using in 8-bit bus access (CR11-B5 = "1"). Digital power supply Address input Address input Address input Address input Address input Address input Address input Address input Power down input "0": Power down reset "1": Normal operation SYNC and BCLK I/O control input "0": SYNC and BCLK become inputs "1": SYNC and BCLK become outputs Digital ground (0.0 V) General-purpose input pin 0 (5 V tolerant input) /Secondary function: Dial pulse detect input pin General-purpose input pin 1 (5 V tolerant input) General-purpose output pin 0 (5 V tolerant output, can be pulled up externally) /Secondary function: Dial pulse transmit pin General-purpose output pin 1 (5 V tolerant output, can be pulled up externally) Analog power supply AMP0 non-inverted input AMP0 inverted input AMP0 output (10 k driving) AMP1 output (10 k driving) AMP1 inverted input Analog signal ground (1.4 V)
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56 57 58 59 60 61 62 63 64
VFRO0 VFRO1 AGND DGND2 XI XO DVDD2 TST3 TST2
O O I O I I
"Hi-z" "Hi-z"
I "H" "0" "0"
AMP2 Output (10 k driving) AMP3 Output (10 k driving) Analog ground (0.0 V) Digital ground (0.0 V) 4.096 MHz crystal oscillator I/F, 4.096 MHz clock input 4.096 MHz crystal oscillator I/F Digital power supply Test control input 3: Normally input "0". Test control input 2: Normally input "0".
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ABSOLUTE MAXIMUM RATINGS
Parameter Analog power supply voltage Digital power supply voltage Analog input voltage Digital input voltage Storage temperature range Symbol VDA VDD VAIN VDIN1 VDIN2 Tstg Conditions Analog pins Normal digital pins 5 V tolerant pins Rating -0.3 to 5.0 -0.3 to 5.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to 6.0 -55 to +150 Unit V V V V V C
RECOMMENDED OPERATING CONDITIONS
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to +60C) Parameter Symbol Conditions Min. Typ. Max. Analog power supply voltage VDA 3.0 3.3 3.6 Digital power supply voltage VDD 3.0 3.3 3.6 Operating temperature range Ta 60 -20 VDD+ VIH1 Digital input pins 2.0 0.3 Digital high level input voltage VIH2 GPI0 and GPI1 pins 2.0 5.5 Digital low level input voltage VIL Digital pins 0.8 -0.3 Digital input rise time tIR Digital pins 2 20 Digital input fall time tIF Digital pins 2 20 Digital output load capacitance CDL Digital pins 50 Capacitance of bypass capacitor Cvref Between AVREF and AGND 2.2+0.1 4.7+0.1 for AVREF Master clock frequency Fmck MCK -0.01% 4.096 +0.01% PCM shift clock frequency Fbclk BCLK (at input) 64 2048 PCM sync signal frequency Fsync SYNC (at input) 8.0 Clock duty ratio DRCLK MCK, BCLK (at input) 40 50 60 BCLK to SYNC tBS 100 (at input) PCM sync timing SYNC to BCLK tSB 100 (at input) PCM sync signal width tWS SYNC (at input) 1BCLK 100
Unit V V C V V V ns ns pF F MHz kHz kHz % ns ns s
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ELECTRICAL CHARACTERISTICS
DC Characteristics
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to +60C) Parameter Symbol Conditions Min. Typ. Max. Standby state ISS 5.0 20.0 (PDNB = "0", VDD = 3.3 V, Ta = 25C) Operating state 1 In the PCM/IF mode (SC_EN = "1", PCMIF_EN = "1", IDD1 45.0 55.0 AFE_EN = "1", TRANS_EN = "1") Connect a 4.096 MHz crystal oscillator Power supply current between XI and XO. Operating state 2 When operating the whole system (SC_EN = "1", PCMIF_EN = "0", IDD2 50.0 65.0 TRANS_EN = "0", AFE_EN = "0") Connect a 4.096 MHz crystal oscillator between XI and XO. Digital input pin IIH Vin = DVDD 0.01 1.0 input leakage current IIL Vin = DGND -1.0 -0.01 Digital I/O pin IOZH Vout = DVDD 0.01 1.0 output leakage current IOZL Vout = DGND -1.0 -0.01 Digital output pins, I/O pins High level output IOH = 4.0 mA VOH 2.2 voltage IOH = 1.0 mA (XO pin) Digital output pins, I/O pins Low level output VOL IOL = -4.0 mA 0.4 voltage IOL = -1.0 mA (XO pin) Input capacitance *1 CIN Input pins 8 12 Unit A
mA
mA
A A A A V
V pF
Note: *1 Guaranteed design value
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Analog Interface
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to +60C) Parameter Symbol Conditions Min. Typ. Max. Unit Input resistance *1 RIN AIN0N, AIN0P, AIN1N 10 M Output load resistance RL GSX0, GSX1, VFRO0, VFRO1 10 k Output load capacitance CL Analog output pins 50 pF Offset voltage VOF VFRO0, VFRO1 40 mV -40 GSX0, GSX1, VFRO0, VFRO1 Output voltage level *2 VO 1.3 Vpp RL = 10 k
Notes: *1 Guaranteed design value *2 -7.7 dBm (600) = 0 dBm0, +3.17 dBm0 = 1.3 Vpp
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AC Characteristics CODEC (Speech CODEC in G.711 (-law) Mode)
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to +60C) Conditions Parameter Symbol Min. Typ. Max. Unit Frequency (Hz) Level (dBm0) 0 to 60 25 dB LT1 300 to 3000 0.20 dB LT2 -0.15 1020 Reference value LT3 Transmit frequency 0 characteristics 3300 0.80 dB LT4 -0.15 3400 0 0.80 dB LT5 3968.75 13 dB LT6 0 to 3000 0.20 dB LR2 -0.15 1020 Reference value LR3 Receive frequency 3300 0.80 dB 0 LR4 -0.15 characteristics 3400 0 0.80 dB LR5 3968.75 13 dB LR6 3 35 dBp SDT1 0 35 dBp SDT2 Transmit signal to noise 35 dBp 1020 SDT3 -30 ratio [*1] 28 dBp SDT4 -40 23 dBp SDT5 -45 3 35 dBp SDR1 0 35 dBp SDR2 Receive signal to noise 35 dBp 1020 SDR3 -30 ratio [*1] 28 dBp SDR4 -40 23 dBp SDR5 -45 3 0.2 dB GTT1 -0.2 Reference value GTT2 -10 Transmit inter-level 0.2 dB 1020 GTT3 -40 -0.2 loss error 0.6 dB GTT4 -50 -0.6 1.2 dB GTT5 -55 -1.2 3 0.2 dB GTR1 -0.2 Reference value GTR2 -10 Receive inter-level loss 0.2 dB 1020 GTR3 -40 -0.2 error 0.6 dB GTR4 -50 -0.6 1.2 dB GTR5 -55 -1.2 Analog input = NIDLT dBm0p -68 Idle channel noise AVREF [*1] PCMI = "1" dBm0p NIDLR -72 Transmit absolute level AVT 1020 0 0.285 0.320 0.359 Vrms [*2] Receive absolute level AVR 1020 0 0.285 0.320 0.359 Vrms [*2] Noise frequency 30 dB PSRRT Power supply noise range: 0 to 50 kHz reject ratio PSRRR 30 dB Noise level: 50mVpp
Notes: *1 Using P-message filter *2 0.320 Vrms = 0 dBm0 = -7.7 dBm (600)
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Gain Setting (Speech CODEC in G.711 (-law) Mode)
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to +60C) Parameter Symbol Conditions Min. Typ. Max. Unit Transmit and receive GAC 1.0 dB -1.0 gain setting accuracy
Tone Output (Speech CODEC in G.711 (-law) Mode)
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to +60C) Parameter Symbol Conditions Min. Typ. Max. Unit Frequency deviation Relative to set frequency 1.5 % fDFT -1.5 Output level Relative to set gain 2.0 dB oLEV -2.0
DTMF Detector, Other Detectors (Speech CODEC in G.711 (-law) Mode)
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to +60C) Parameter Symbol Conditions Min. Typ. Max. Unit Detect level accuracy dLAC Relative to set detect level 2.5 dB -2.5
Echo Canceller
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to +60C) Parameter Symbol Conditions Min. Typ. Max. Unit In the analog I/F mode 35 In the PCM I/F (16-bit linear) mode Echo attenuation eRES dB In the PCM I/F (G.711) mode 30 Erasable echo delay time tECT 32 ms
Measurement method
Echo Canceller ATT E.R.L (echo return loss) LPF 5 kHz White noise generator Sin Sout Level Meter
Delay Echo delay time
Rout
Rin
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PDNB, XO, AVREF Timings
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to +60C) Parameter Symbol Conditions Min. Typ. Max. Unit Power down signal pulse tPDNB PDNB pin 1 s width Oscillation start-up time txtal 100 ms 2+ AVREF = 1.4 (90%) AVREF rise time tAVREF 600 ms C5 = 4.7 F, C6 = 0.1 F (See Fig. 9.) Initialization mode start-up tINIT 1 s time
* is a value that depends on the oscillation stabilizing time when using a crystal oscillator.
VDD DVDD, AVDD PDNB tPDNB 0V VDD 0V VDD XO 0V txtal About 1.4 V 0V tAVREF CR5-B7 (READY) tINIT Initialization mode "0" "1"
AVREF
Fig. 1 PDNB, XO, and AVREF timings
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PCM I/F Mode
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to +60C) Parameter Symbol Conditions Min. Typ. Max. Unit Bit clock frequency fBCLK CDL = 20pF(at output) 64 +0.1% kHz -0.1% Bit clock duty ratio dBCLK CDL = 20pF(at output) 45 50 55 % CDL = 20pF(at output) 8 +0.1% kHz Sync signal frequency fSYNC -0.1% CDL = 20pF(at output) dSYNC1 12.4 12.5 12.6 % At 64 kHz output Sync signal duty ratio CDL = 20pF(at output) dSYNC2 6.24 6.25 6.26 % At 128 kHz output BCLK to SYNC tBS 100 ns Transmit/receive signal sync (at output) timing SYNC to BCLK tSB 100 ns (at output) Input setup time tDS 100 -- ns Input hold time tDH 100 -- ns tSDX 100 ns Digital output delay time PCMO pin tXD1 100 ns Pull-up, pull-down resistors tXD2 100 ns RDL = 1 k, CDL = 50 pF Digital output hold time tXD3 100 ns
BCLK
0 tBS
1 tSB
2
3
4
5
6
7
8
-
16
tWS
SYNC
tDS tDH LSB G.726 LSB G.711 LSB 16-bit linear
PCMI
MSB
Fig. 2 PCM I/F mode input timing (long frame)
BCLK
0 tBS
1 tSB
2
3
4
5
6
7
8
9
-
17
tWS
SYNC
tDS tDH LSB G.726 LSB G.711 LSB 16-bit linear
PCMI
MSB
Fig. 3 PCM I/F mode input timing (short frame)
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BCLK
0 tBS
1 tSB
2
3
4
5
6
7
8
9
-
17
tWS
SYNC
tSDX tXD1 MSB tXD2 LSB G.726 LSB G.711 tXD3 LSB 16-bit linear tXD3
PCMO
Hi-z
Fig. 4 PCM I/F mode output timing (long frame)
BCLK
0 tBS
1 tSB
2
3
4
5
6
7
8
9
10
-
18
tWS
SYNC
tXD1 Hi-z tXD2 LSB G.726 LSB G.711 tXD3 LSB 16-bit linear tXD3
PCMO
MSB
Fig. 5 PCM I/F mode output timing (short frame)
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Control Register Interface
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to +60C) Parameter Symbol Conditions Min. Typ. Max. Unit Address setup time tAS 10 ns Address hold time tAH 10 ns Write data setup time tWDS 10 ns Write data hold time tWDH 10 ns CSB setup time tCS 10 ns CSB hold time tCH 10 ns CL = 50 pF WRB pulse width tWW 10 ns Read data output delay time tRDD 20 ns Read data output hold time tRDH 3 ns RDB pulse width tRW 25 ns CSB disable time tCD 10 ns
A7-A0 Input tAS D7-D0 I/O tWDS CSB Input tCS WRB Input
A1 tAH D1 Input tWDH tAS
A2 tAH D2 Output tRDD tRDH
tCH
tCD
tCS
tCH
tWW RDB Input Write timing
tRW
Read timing
Fig. 6 Control register interface
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Transmit and Receive Buffer Interface (in Frame Mode)
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to +60C) Parameter Symbol Conditions Min. Typ. Max. Unit FR1B setup time tF1S 3 ns FR1B output delay time tF1D 20 ns Address setup time tAS 10 ns Address hold time tAH 10 ns Write data setup time tWDS 10 ns Write data hold time tWDH 10 ns CSB setup time tCS 10 ns CSB hold time tCH 10 ns CL = 50 pF WRB pulse width tWW 10 ns FR0B setup time tF0S 3 ns FR0B output delay time tF0D 20 ns Read data output delay time tRDD 30 ns Read data output hold time tRDH 3 ns RDB pulse width tRW 35 ns CSB disable time tCD 10 ns
FR0B Output tF0S FR1B Output tF1S A7-A0 Input tAS D15-D0 I/O tWDS CSB Input WRB Input tCS tCH tCD tCS tCH D1 Input tWDH tRDD A1 tAH tAS tF1D A2 tAH D2 Output tRDH tF0D
tWW RDB Input Write timing
tRW
Read timing
Fig. 7 Transmit and receive buffer interface (in frame mode)
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Transmit and Receive Buffer Interface (in DMA Mode)
(Unless otherwise specified, AVDD = 3.0 to 3.6 V, DVDD0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V, Ta = -20 to +60C) Parameter Symbol Conditions Min. Typ. Max. Unit DMARQ1B setup time tDR1S 3 ns tDR1RD 25 ns DMARQ1B output delay time tDR1FD 25 ns Address setup time tAS 10 ns Address hold time tAH 10 ns Write data setup time tWDS 10 ns Write data hold time tWDH 10 ns ACK setup time tAKS 10 ns ACK hold time tAKH 10 ns CL = 50 pF WRB pulse width tWW 10 ns DMARQ0B setup time tDR0S 3 ns tDR0RD 20 ns DMARQ0B output delay time tDR0FD 25 ns Read data output delay time tRDD 30 ns Read data output hold time tRDH 3 ns RDB pulse width tRW 35 ns ACKB disable time tAD 10 ns
DMARQ0B Output tDR0S tDR0RD DMARQ1B Output tDR1S A7-A0 Input tAS D15-D0 I/O tWDS ACK0B Input tAKS ACK1B Input WRB Input tAKS tAKH tAD tAKH D1 Input tWDH tRDD tDR1FD tDR1RD A1 tAH tAS D2 Output tRDH A2 tAH tDR0FD
tWW RDB Input Write timing
tRW
Read timing
Fig. 8 Transmit and receive buffer interface (in DMA mode)
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PIN FUNCTION DESCRIPTIONS
AIN0N, AIN0P, GSX0, AIN1N, GSX1 These are the analog transmit input and transmit level adjust pins. Each of AIN0N and AIN1N is connected to each of the inverting input pins of the built-in transmit amplifiers AMP0 and AMP1, and AIN0P is connected to the non-inverting input pin of AMP0. In addition, GSX0 and GSX1 are connected to the output pins of AMP0 and AMP1, respectively. The selection between AMP0 and AMP1 is made by CR10-B0. See Fig. 9 for the method of making level adjustment. During the power down mode (when PDNB = "0" or CR0-B7 = "1"), the outputs of GSX0 and GSX1 go to the high impedance state. If AMP0 is not used in the specific application of this LSI, short GSX0 with AIN0N and connect AIN0P with AVREF. When AMP1 is not used, short GSX1 with AIN1N. Notice: It is recommended to select the amplifier to be used before the conversation starts, since a small amount of noise will be generated if the amplifier selection is changed while conversation is in progress. VFRO0, VFRO1 These are analog receive output pins and are connected to the output pins of the built-in receive amplifiers AMP2 and AMP3, respectively. The output signals of VFRO0 and VFRO1 can be selected using CR10-B1 and CR10-B2, respectively. When selected ("1"), the received signal will be output, and when deselected ("0"), the AVREF signal (about 1.4 V) will be output. In the power down mode, these pins will be in the high impedance state. It is recommended to use these output signals via DC coupling capacitors. Notice: It is recommended to select the amplifier to be used before the conversation starts, since a small amount of noise is generated if the output selection is changed while the conversation is in progress. At the time of resetting or releasing from the reset state, it is recommended to select the AVREF as outputs of VFRO0 and VFRO1.
GSX0 R2 Gain = R2/R1 <= 63(+36dB) R1 : Variable R2 : Max 500k C1 R1 AIN0N 10k
AIN0P
AMP0
CR10-B0
A/D
GSX1 Gain = R4/R3 <=63(+36dB) R1 : Variable R2 : Max 500k R4 C2 R3 AIN1N 10
AMP1 CR10-B1
Out : Max 1.3Vp-p
C3 VFRO0
10k
D/A
AMP2 CR10-B2
Out : Max 1.3Vp-p
C4
VFRO1
10k
AMP3
AVREF C5 + 2.2 to 4.7F
VREF
C6 0.1F
Fig. 9 Analog interface
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OKI Semiconductor
ML7074-001 GA
AVREF This is the output pin for the analog signal ground potential. The output potential at this pin will be about 1.4 V. Connect a 2.2 to 4.7 F (aluminum electrolytic type) capacitor and a 0.1 F (ceramic type) capacitor in parallel between this pin and the GND pin as bypass capacitors. The output at the AVREF pin goes to 0.0 V in the power down mode. The voltage starts rising after the power down mode is released (PDNB = "1" and also CR0-B7 = "0"). The rise time is about 0.6 sec. XI, XO These are the pins for either connecting the crystal oscillator for the master clock or for inputting an external master clock signal. The oscillations of the master clock oscillator will be stopped during a power down due to the PDNB signal or during a software power down due to CR0-B7 (SPDN). The oscillations start when the power down condition is released, and the internal clock supply of the LSI will be started after counting up the oscillation stabilization period (of about 16 ms). Examples of crystal oscillator connection and external master clock input are shown in Fig. 10.
CR0-B7 (SPDN) PDNB CR0-B7 (SPDN) PDNB
To internal circuits
To internal circuits
XI
R X'tal
XO
XI 4.096 MHz
XO Open
C1
C2
X'tal(4.096 MHz) Daishinku Co., Ltd. AT-49
C1 5pF
C2 10pF
R 1M
Fig. 10 Examples of oscillator circuit and clock input PDNB This is the power down control input pin. The power down mode is entered when this pin goes to "0". In addition, this pin also has the function of resetting the LSI. In order to prevent wrong operation of the LSI, carry out the initial power-down reset after switching on the power using this PDNB pin. Also, keep the PDNB pin at "0" level for 1 s or more to initiate the power down state. Further, it is possible to carry out a power down reset of the LSI when the power is being supplied by performing control of CR0-B7 (SPDN) in the sequence "0" "1" "0". The READY signal (CR5-B7) goes to "1" about 1.0 second after the power down mode is released thereby entering the mode of setting various functions (initialization mode). See Fig. 1 for the timings of PDNB and AVREF, XO, and the initialization mode. Notice: At the time of switching on the power, start from the power down mode using PDNB. DVDD0, DVDD1, DVDD2, AVDD These are power supply pins. DVDD0, 1, 2 are the power supply pins for the digital circuits while AVDD is the power supply pin for the analog circuits of the LSI. Connect these pins together in the neighborhood of the LSI and connect as bypass capacitors a 10 F electrolytic capacitor and a 0.1 F ceramic capacitor in parallel between the DGND and AGND pins. DGND0, DGND1, DGND2, AGND These are ground pins. GDND0, 1, 2 are the ground pins for the digital circuits and AGND is the ground pin for the analog circuits of the LSI. Connect these pins together in the neighborhood of the LSI.
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FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
TST0, TST1, TST2, TST3 These are input pins for testing purposes only. Keep the inputs to these pins at the "0" level during normal use conditions. INTB This is the interrupt request output pin. An "L" level is output for a duration of about 1.0 sec at this pin when there is a change in state of an interrupt cause. This output will be maintained at the "H" level when there is no change in state of any of the interrupt causes. The actual interrupt cause generating the interrupt can be verified by reading CR3 and CR4. The different interrupt causes are described below. * Underflow error (CR3-B0) An interrupt is generated when an internal read from the receive buffer occurs before the writing into the receive buffer from the MCU has been completed. An interrupt is generated when a normal writing is made in the receive buffer by the MCU and the underflow error is released. * Overrun error (CR3-B1) An interrupt is generated when an internal write of the next data into the transmit buffer occurs before the transmit buffer data read out from the MCU has been completed. An interrupt is generated when a normal read out is made from the transmit buffer by the MCU and the overrun error is released. * When a dial pulse is detected (CR4-B6). * When a DTMF signal is detected (CR4-B4). * When DTMF_CODEC0, 1, 2, 3 are detected (CR4-B0, B1, B2, B3). An interrupt is generated when a DTMF signal is detected. An interrupt is generated when there is a change from the DTMF signal detected state to the no-detected state. An interrupt is generated when there is a change in the detected code (CR4-B0, B1, B2, B3) in the condition in which a DTMF signal is being detected. * When TONE0 is detected (CR3-B3). An interrupt is generated when a 1650 Hz tone signal is detected. An interrupt is generated when there is a change to the non-detection condition in the tone signal detection condition. * When TONE1 is detected (CR3-B4). An interrupt is generated when a 2100 Hz tone signal is detected. An interrupt is generated when there is a change to the non-detection condition in the tone signal detection condition. * When FGEN_RQ is generated (CR3-B6). An interrupt is generated when the FSK generator makes a request for the next data to be transmitted. An interrupt is generated when there is a change from the condition in which the FSK generator is requesting for transmission data to the condition in which there is no request for internal fetch of the data to be transmitted next. * When DSP_ERR is detected (CR3-B7). An interrupt is generated when any error occurs in the DSP inside the LSI.
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FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
A0 to A7 These are the address input pins for use during an access of the frame, DMA, or control registers. The different addresses will be the following. Transmit buffer (TX Buffer) A7 to A0 = 10xxxxxxb (the lower 6 bits are not valid) Receive buffer (RX Buffer) A7 to A0 = 01xxxxxxb (the lower 6 bits are not valid) Control register (CR) A7 to A0 = 00xxxxxxb D0 to D15 These are the data input/output pins for use during an access of the frame, DMA, or control registers. Connect pull-up resistors to these pins since they are I/O pins. When the 8-bit bus access method is selected by CR11-B5, only D0 to D7 become valid. Since the higher 8 bits D8 to D15 will always be in the input state when the 8-bit bus access method is selected (CR11-B5 = "1"), tie them to "0" or "1" inputs. CSB This is the chip select input pin for use during a frame or control register access. RDB This is the read enable input pin for use during a frame, DMA, or control register access. WRB This is the write enable input pin for use during a frame, DMA, or control register access.
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FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
FR0B (DMARQ0B) * FR0B (In frame mode, CR11-B7 = "0") This is the transmit frame output pin which outputs the signal when the transmit buffer is full during frame access. This pin outputs an "L" level when the transmit buffer becomes full, and maintains that "L" level output until a specific number of words are read out from the MCU. * DMARQ0B (In DMA mode, CR11-B7 = "1") This is the DMA request output pin which outputs the signal when the transmit buffer is full during DMA access. This output becomes "L" when the transmit buffer becomes full, and returns to the "H" level automatically on the falling edge of the read enable signal (RDB = "1" "0") when there is an acknowledgement signal (ACK0B = "0") from the MCU. This relationship is repeated until a specific number of words are read out from the MCU. FR1B (DMARQ1B) * FR1B (In frame mode, CR11-B7 = "0") This is the receive frame output pin which outputs the signal when the receive buffer is empty during frame access. This pin outputs an "L" level when the receive buffer becomes empty, and maintains that "L" level output until a specific number of words are written from the MCU. * DMARQ1B (In DMA mode, CR11-B7 = "1") This is the DMA request output pin which outputs the signal when the receive buffer is empty during DMA access. This output becomes "L" when the receive buffer becomes empty, and returns to the "H" level automatically on the falling edge of the write enable signal (WRB = "1" "0") when there is an acknowledgement signal (ACK1B = "0") from the MCU. This relationship is repeated until a specific number of words are written from the MCU. ACK0B This is the DMA acknowledgement input pin for the DMARQ0B signal during DMA access of the transmit buffer and becomes valid in the DMA mode (CR11-B7 = "1"). Tie this pin to "1" when using this LSI in the frame access mode (CR11-B7 = "0"). ACK1B This is the DMA acknowledgement input pin for the DMARQ1B signal during DMA access of the receive buffer and becomes valid in the DMA mode (CR11-B7 = "1"). Tie this pin to "1" when using this LSI in the frame access mode (CR11-B7 = "0"). GPI0, GPI1 These are general-purpose input pins. The state ("1" or "0") of each of these GPI0 and GPI1 pins can be read out respectively from CR16-B0 and CR16-B1. Further, GPI0 becomes the input pin for the dial pulse detector (DPDET) in the secondary functions. GPO0, GPO1 These are general-purpose output pins. The values set in CR17-B0 and CR17-B1 are output at these pins GPO0 and GPO1, respectively. Further, GPO0 becomes the output pin for the dial pulse generator (DPGEN) in the secondary functions.
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FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
CLKSEL This is the input/output control input pin of SYNC and BCLK. The pin becomes input at "0" level and output at "1" level. SYNC This is the 8 kHz sync signal input/output pin of PCM signals. When CLKSEL is "0", input continuously an 8 kHz clock synchronous with BCLK. Further, when CLKSEL is "1", this pin outputs an 8 kHz clock synchronous with BCLK. Long frame synchronization is used when CR0-B1 (LONG/SHORT) is "0" and short frame synchronization is used when it is "1". BCLK This is the shift clock input/output pin for the PCM signal. When CLKSEL is "0", it is necessary to input to this pin a clock signal that is synchronous with SYNC. Input a 64 to 2048 kHz clock when the G.711 mode or the G.726 mode has been selected, and input a 128 to 2048 kHz clock when the 16-bit linear mode has been selected. When CLKSEL is "1", this pin outputs a clock that is synchronous with SYNC. This pin outputs a 64 kHz clock when the G.711 mode or the G.726 mode has been selected, and outputs an 128 kHz clock when the 16-bit linear mode or G.729.A mode has been selected. Note: The input/output control and frequencies of the above SYNC and BLCK signals will be as shown in Table 1 below. Table 1 Input/output control of SYNC and BCLK
CLKSEL SYNC Remarks Input a continuous clock after starting the power supply. Input Input a 64 to 2048 kHz clock when G.711 or G.726 is (64 kHz to 2048 kHz) selected. Input a 128 to 2048 kHz clock when 16-bit linear mode is selected. An "L" level is output during the power down mode. A 64 kHz clock is output when G.711 or G.726 is Output selected. (64 kHz or 128 kHz) A 128 kHz clock is output when G.729.A or 16-bit linear mode is selected. BCLK
"0"
Input (8 kHz)
"1"
Output (8 kHz)
PCMO This is the PCM signal output pin for the transmitting section. The PCM signal is output in synchronization with the rising edges of SYNC and BCLK. The PCMO outputs the data only during the valid data segment in the selected coding format and goes to the high impedance state during all other segments. The basic timing chart of the PCM I/F mode is shown in Fig. 11. The PCMO output will be in the high impedance state when the mutual conversion function is not used (CR11-B0 = "0") or when the PCM I/F mode is not used (CR12-B0 = "0"). PCMI This is the PCM signal input pin for the receiving section. The data is entered starting from the MSB by shift on the falling edge of BCLK. The basic timing chart of the PCM I/F mode is shown in Fig. 11. Fix input with "0" or "1" when the mutual conversion function is not used (CR11-B0 = "0") or when the PCM I/F mode (CR12-B0 = "0") is not used.
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FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
16-Bit linear Long frame synchronization mode (CR0-B1 = "0") SYNC (IN/OUT) BCLK (IN/OUT) PCMI Hi-z D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 Hi-z Hi-z Hi-z
PCMO
16-Bit linear Short frame synchronization mode (CR0-B1 = "1") SYNC (IN/OUT) BCLK (IN/OUT) PCMI
PCMO
G.711 (-law, A-law) Long frame synchronization mode (CR0-B1 = "0") SYNC (IN/OUT) BCLK (IN/OUT) PCMI Hi-z D7 D6 D5 D4 D3 D2 D1 D0
PCMO
G.711 (-law, A-law) Short frame synchronization mode (CR0-B1 = "1") SYNC (IN/OUT) BCLK (IN/OUT) PCMI Hi-z D7 D6 D5 D4 D3 D2 D1 D0
PCMO
G.726 (32 kbps) Long frame synchronization mode (CR0-B1 = "0") SYNC (IN/OUT) BCLK (IN/OUT) PCMI Hi-z D3 D2 D1 D0
PCMO
G.726 (32 kbps) Short frame synchronization mode (CR0-B1 = "1") SYNC (IN/OUT) BCLK (IN/OUT) PCMI D3 D2 D1 D0
PCMO
Fig. 11 PCM I/F mode timing diagram
D3 D2 D1 D0
Hi-z
Hi-z
D3 D2 D1 D0
Hi-z
D7 D6 D5 D4 D3 D2 D1 D0
Hi-z
D7 D6 D5 D4 D3 D2 D1 D0
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
:
:
:
:
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FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
example of Configuration Analog I/F mode
TONE_DET0 TONE_DET1
TONE0_DET TONE1_DET DTMF_DET DTMF_CODE[3:0]
DTMF_REC GSX0
10k
Speech Codec Linear PCM Codec
A/D BPF
Bus Control Unit TX Buffer0 TX Buffer1
AIN0N AIN0P GSX1
10k AMP0
Echo Canceller
TXGAIN Sin LPAD Sout
Encoder G.729.A G.726 G.711 G.729.A
+ ATTs
Center Clip
GPAD
AIN1N
AMP1 STGAIN
AFF
TONE_GEN (TONEA/B)
Decoder G.729.A
10k
VFRO0
AMP2
D/A
LPF
Rout
ATTr
Rin
RXGAIN
G.726 G.711
FSK_GEN
RX Buffer0 RX Buffer1 8b A0-A7 16b
Frame/DMA Controller
10k
VFRO1
AMP3
G.729.A
Codec AVREF
VREF
Decoder
G.711
PCMI
S/P G.726
TIMER DPGEN
CR17-B0(GPO0) CR16-B0(GPI0)
Encoder PCMO SYNC BCLK CLKSEL Serial I/F XI XO DVDD1 DVDD0 DGND0 DGND1 DVDD2 DGND2 AGND AVDD
Function stopped Cannot be used P/S G.711 G.726
PLL
CKGN
MCK SYNC(8kHz)
DPDET
Control Register
D0-D15 CSB RDB WRB FR0B FR1B ACK0B ACK1B
OSC
Power
DP_DET DTMF_DET DTMF_CODE[3:0] TONE0_DET TONE1_DET DP_DET
INT
INTB
Example of settings in the initialization mode CR15 = 40 CR11 = 00h (Frame/10 ms/16B/Speech CODEC = G.729.A) Various settings CR0 = 09h (OPE_STAT = "1")
GPI0 GPI1 GPO0 GPO1
PDNB
TST0 TST1 TST2 TST3
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FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
PCM I/F Mode
TONE_DET0 TONE_DET1
TONE0_DET TONE1_DET DTMF_DET DTMF_CODE[3:0]
DTMF_REC GSX0
10k
Speech Codec Linear PCM Codec
A/D BPF
Bus Control Unit TX Buffer0 TX Buffer1
AIN0N AIN0P GSX1
10k AMP0
Echo Canceller
TXGAIN Sin LPAD Sout
Encoder G.729.A G.726 G.711 G.729.A
+ ATTs
Center Clip
GPAD
AIN1N
AMP1 STGAIN
AFF
TONE_GEN (TONEA/B)
Decoder G.729.A
10k
VFRO0
AMP2
D/A
LPF
Rout
ATTr
Rin
RXGAIN
G.726 G.711
FSK_GEN
RX Buffer0 RX Buffer1 8b A0-A7 16b
Frame/DMA Controller
10k
VFRO1
AMP3
G.729.A
Codec AVREF VRE F
S/P G.726
Decoder
G.711
PCMI
TIMER DPGEN
CR17-B0(GPO0) CR16-B0(GPI0)
Encoder PCMO SYNC BCLK CLKSEL Serial I/F DVDD1 DVDD0 DGND0 DGND1 DVDD2 DGND2 AGND AVDD
P/S G.711 G.726
PLL
CKGN
MCK SYNC(8kHz)
DPDET
Control Register
D0-D15 CSB RDB WRB FR0B FR1B ACK0B ACK1B
OSC
Power
DP_DET DTMF_DET DTMF_CODE[3:0] TONE0_DET TONE1_DET DP_DET
INT
INTB
Function stopped Cannot be used
Examples of settings in the initialization mode CR15 = 40 CR10 = 00h (VFRO1 = AVREF/VFRO0 = AVREF) CR11 = 00h (Frame/10 ms/16B/PCMIF = 16-bit linear) CR12 = 01h (Speech CODEC = G.729.A/PCMIF_EN = "1") Various settings CR0 = 29h (AFE_EN = Power down/LONG/OPE_STAT = "1")
GPI0 GPI1 GPO0 GPO1
XI
XO
PDNB
TST0 TST1 TST2 TST3
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FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
G.729.A G.726 Mutual Conversion
TONE_DET0 TONE_DET1
TONE0_DET TONE1_DET DTMF_DET DTMF_CODE[3:0]
DTMF_REC GSX0
10k
Speech Codec Linear PCM Codec
A/D BPF
Bus Control Unit TX Buffer0 TX Buffer1
AIN0N AIN0P GSX1
10k AMP0
Echo Canceller
TXGAIN Sin LPAD Sout
Encoder G.729.A G.726 G.711 G.729.A
+ ATTs
Center Clip
GPAD
AIN1N
AMP1 STGAIN
AFF
TONE_GEN (TONEA/B)
Decoder G.729.A
10k
VFRO0
AMP2
D/A
LPF
Rout
ATTr
Rin
RXGAIN
G.726 G.711
FSK_GEN
RX Buffer0 RX Buffer1 8b A0-A7 16b
Frame/DMA Controller
10k
VFRO1
AMP3
G.729.A
Codec AVREF
VREF
Decoder
G.711
PCMI
S/P G.726
TIMER DPGEN
CR17-B0(GPO0) CR16-B0(GPI0)
Encoder PCMO SYNC BCLK CLKSEL Serial I/F DVDD1 DVDD0 DGND0 DGND1 DVDD2 DGND2 AGND AVDD
P/S G.711 G.726
PLL
CKGN
MCK SYNC(8kHz)
DPDET
Control Register
D0-D15 CSB RDB WRB FR0B FR1B ACK0B ACK1B
OSC
Power
DP_DET DTMF_DET DTMF_CODE[3:0] TONE0_DET TONE1_DET DP_DET
INT
INTB
Function stopped Cannot be used
Examples of settings in the initialization mode CR15 = 40 CR11 = 05h (Frame/10 ms/16B/G.726/TRANS_EN= "1") CR10 = 00h (VFRO1 = AVREF/VFRO0 = AVREF) Various settings CR0 = 29h (AFE_EN = Power down/LONG/OPE_STAT = "1")
GPI0 GPI1 GPO0 GPO1
XI
XO
PDNB
TST0 TST1 TST2 TST3
27/31
FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
EXAMPLE OF APPLICATION CIRCUIT
1.4V 50 51 Analog input 52 53 54 55 AIN0P AIN0N GSX0 GSX1 AIN1N AVREF A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 41 40 39 38 37 36 35 34 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 +3.3V ACK0B ACK1B FR0B FR1B INTB CSB RDB WRB 8 9 10 11 12 13 14 15
56 Analog output
Generalpurpose input pins Generalpurpose output pins
VFRO0 VFRO1 GPI0 GPI1 GPO0 GPO1
57 45 46 47 48 +3.3V 43 4 3 5 6 42
MCU I/F
ML7074-001
CLKSEL PCMI PCMO BCLK SYNC PDNB
open open open Power down control 4.096 MHz crystal oscillator
PCM I/F
60 61
XI XO
+3.3V 7 33 62 49 16 44 59 58 DVDD0 DVDD1 DVDD2 AVDD DGND0 DGND1 DGND2 AGND TST3 TST2 TST1 TST0 63 64 1 2
Conditions: - When using analog interface - Frame mode - SYNC and BCLK are output (CLKSEL="1")
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FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
PACKAGE DIMENSIONS
(Unit: mm)
QFP64-P-1414-0.80-BK
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (J5m) 0.87 TYP. 6/Feb. 23, 2001
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
REVISION HISTORY
Document No. FEDL7074-001-01 Date Oct. 15, 2002 Page Previous Current Edition Edition - - Final edition 1 Description
30/31
FEDL7074-001DIGEST-01
OKI Semiconductor
ML7074-001 GA
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd.
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